Modern high throughput systems utilize multiple high bandwidth input/output interfaces to form a signaling network between compute units, memory devices, and storage devices. For example, Peripheral Component Interconnect Express (PCI-E) connects multiple periphery devices to central processing units (CPUs) and graphics processing units (GPUs). These interfaces may comprise multiple serial data buses that operate at high frequency.
Pulse amplitude modulation (PAM) may be utilized on a multi-lane serial data bus to transfer multiple bits of data simultaneously by encoding the data as different voltage levels. Here, “lane” refers to a single data lane of a serial data bus. A “data burst” refers to bits placed on the data lanes of a serial data bus in a same bus clock interval, i.e., in parallel.
An example of PAM communication is PAM-4. During each bus clock interval, PAM-4 encodes two bits of data (00, 01, 10, 11) on each data lane of a serial data bus as one of four different voltage levels (symbols). Because two bits are encoded into each bus clock interval on each data lane, PAM-4 ideally enables twice the bandwidth compared to conventional two-level (e.g., PAM-2) signaling on serial data buses operating at comparable bus clock frequencies. PAM-4 symbols utilize four different voltage levels and therefore there is less voltage-level distinction between symbol values in PAM-4 compared to PAM-2. This makes PAM-4 communications more vulnerable to interference effects such as coupling noise between data lanes on a serial data bus, and power supply noise, which reduces the signal to noise ratio (SNR).
One mechanism to mitigate these noise effects is to utilize Data Bus Inversion (DBI). For a given data burst, DBI reduces the total extent of voltage level transitions across the data lanes of a serial data bus by up to half by intelligently setting the polarity of the bits in each data burst on the serial data bus. DBI requires an additional metadata bit per data burst to transfer the data burst polarity setting (non-inverted data burst, or inverted data burst) to the receiver. This metadata bit is often transmitted on an extra data lane that is separate from the data lanes (each also one data lane, typically) of the serial data bus.
Many serial data buses comprise only a single data lane between the transmitter and the receiver. Adding an additional metadata data lane can thus result in up to 100% overhead in the number of data lanes required for the serial data bus.